An information handling system (IHS) may include multiple processors for processing, handling, communicating or otherwise manipulating information. Each processor may itself include multiple processor cores that work together to process information such as instructions and data. A processor or processor core may include multiple execution units that work together to complete one or more instructions every clock cycle. The processor core or cores function cooperatively with a high level operating system (OS) or other software that manages the processing of instructions.
Instructions within the IHS are subject to stalls, delays, or other events that may negatively impact or otherwise interrupt instruction execution and thus delay completion. Instruction completion stalls reduce the overall performance of information handling systems. Under one definition, a stall cycle is any IHS clock cycle in which an instruction or instruction group does not complete. Completion stall analysis attempts to determine why a processor does not complete the execution of instructions in a timely fashion. In other words, completion stall analysis provides a method to determine the cause of instruction completion stalls, thus enabling potential corrective action by software or hardware. These instruction completion stalls may include a data cache miss (waiting for data from memory), a data dependency (waiting for data from another instruction completion), an execution delay (waiting for the completion of the current instruction), and other stall events. Determining the exact cause of instruction completion stalls can be particularly difficult in an information handling system that employs multiple processors with multiple instructions that execute simultaneously in a speculative and/or out-of-order manner. The precise cause of an instruction completion stall may not be known until the instruction completion stall ends and the particular stalled instruction finally completes execution. Current completion stall analysis systems may attempt to guess the cause of instruction completion stalls. Such a speculative completion stall analysis may use speculative counters to assist software in determining the ultimate cause of instruction completion stalls. One known methodology provides an aggregate stall count of the number of instructions that experience completion delays.
What is needed is a method and apparatus that provides more detailed information regarding the instructions that experience completion delays and that addresses the problems described above.